In-cell facial recognition display panel, method and liquid crystal display

ABSTRACT

An in-cell facial recognition display panel, a method, and a liquid crystal display are disclosed. A facial recognition sub pixel is provided with a facial recognition module which is configured to capture a facial image. A display chip and facial recognition chip is arranged at one terminal of a non-display area. The display chip drives a panel display. The facial recognition chip drives the facial recognition sub pixel to capture the facial image. The present disclosure facilitates the design of a comprehensive screen, the improvement of the screen production yield, and the economy of the entire device.

BACKGROUND 1. Field of the Disclosure

The present disclosure relates to the display panel technology, and moreparticularly, to an in-cell facial recognition display panel, a method,and a liquid crystal display (LCD).

2. Description of the Related Art

With the development of the facial recognition technology, majorcellphone manufacturers are deploying facial recognition. Facialrecognition of the related art requires a separate facial recognitionsensor, which occupies some space, so it is not conducive to full screendesign. Embedding the facial recognition function into the liquidcrystal panel is increasingly valued by panel manufacturing companiesbecause of the low cost of manufacturing materials and the advantage ofbeing more comprehensive screen design. A plan of the related art aboutthe arrangement of a facial recognition sensor is to place the facialrecognition sensor in a groove by digging grooves in the top of thescreen.

Please refer to FIG. 1 illustrating a schematic diagram of a displaypanel of the related art. The display panel of the related art includesa display area 11 and a non-display area 12. A display chip 121 isdisposed at one terminal of the non-display area 12. The display chip121 drives the display panel to operate normally. Pixels 111 aredisposed in the display area 11. Each of the pixels 111 includes an Rsub pixel (Sub Pixel R), a G sub pixel (Sub Pixel G), and a B sub pixel(Sub Pixel B). All of the pixels 111 are distributed throughout thedisplay area 11 in an array.

The facial recognition method of the related art that a facialrecognition sensor is arranged in a groove which is dug in the top ofthe screen has the disadvantage of affecting the appearance and failingto design a full screen. Besides, the design of screen trenching isdifficult. The screen production yield and the yield rate may belowered. The screen cost may increase. In addition, additional facialrecognition devices also increase the cost of the entire device.

SUMMARY

An object of the present disclosure is to provide an in-cell facialrecognition display panel, a method, and a liquid crystal display (LCD),which facilitates the design of a comprehensive screen, the improvementof the screen production yield, and the economy of the entire device.

According to a first aspect of the present disclosure, an in-cell facialrecognition display panel comprises a display area and a non-displayarea. A plurality of pixels are distributed in an array in the displayarea. Each of the plurality of pixels comprises a red sub pixel, a greensub pixel, a blue sub pixel, and a facial recognition sub pixel. Thefacial recognition sub pixel is provided with a facial recognitionmodule which is configured to capture a facial image. A display chip andfacial recognition chip is arranged at one terminal of the non-displayarea. The display chip is separately connected to the red sub pixel, thegreen sub pixel, and the blue sub pixel, and configured to drive the redsub pixel, the green sub pixel, and the blue sub pixel to perform paneldisplay. The facial recognition chip is connected to the facialrecognition sub pixel and configured to drive the facial recognition subpixel to capture the facial image.

According to a second aspect of the present disclosure, a panel displayand facial recognition method performed by an in-cell facial recognitiondisplay panel is provided. The in-cell facial recognition display panelcomprises a display area and a non-display area. A plurality of pixelsare distributed in an array in the display area. Each of the pluralityof pixels comprises a red sub pixel, a green sub pixel, a blue subpixel, and a facial recognition sub pixel. The facial recognition subpixel is provided with a facial recognition module which is configuredto capture a facial image. A display chip and facial recognition chip isarranged at one terminal of the non-display area. The display chip isseparately connected to the red sub pixel, the green sub pixel, and theblue sub pixel, and configured to drive the red sub pixel, the green subpixel, and the blue sub pixel to perform panel display. The facialrecognition chip is connected to the facial recognition sub pixel andconfigured to drive the facial recognition sub pixel to capture thefacial image. The panel display and facial recognition method comprises:sequentially outputting a high voltage level to all scanning signallines in the display panel to turn on thin film transistors (TFTs) whichall red sub pixels, green sub pixels, blue sub pixels, and facialrecognition sub pixels in corresponding rows correspond to; inputtingdisplay voltage imposed on the corresponding row with a display chip tothe corresponding red sub pixel in the corresponding row through allfirst data signal lines; inputting the display voltage imposed on thecorresponding row with the display chip to the corresponding green subpixel in the corresponding row through all second data signal lines;inputting the display voltage imposed on the corresponding row with thedisplay chip to the corresponding blue sub pixel in the correspondingrow through all third data signal lines; and reading information about afacial image in the corresponding row with a facial recognition chipfrom the corresponding facial recognition sub pixel in the correspondingrow through all fourth data signal lines.

According to a third aspect of the present disclosure, a liquid crystaldisplay comprises an in-cell facial recognition display panel. Thein-cell facial recognition display panel comprises a display area and anon-display area. A plurality of pixels are distributed in an array inthe display area. Each of the plurality of pixels comprises a red subpixel, a green sub pixel, a blue sub pixel, and a facial recognition subpixel. The facial recognition sub pixel is provided with a facialrecognition module which is configured to capture a facial image. Adisplay chip and facial recognition chip is arranged at one terminal ofthe non-display area. The display chip is separately connected to thered sub pixel, the green sub pixel, and the blue sub pixel, andconfigured to drive the red sub pixel, the green sub pixel, and the bluesub pixel to perform panel display. The facial recognition chip isconnected to the facial recognition sub pixel and configured to drivethe facial recognition sub pixel to capture the facial image.

The disclosure has advantages as follows:

(1) It is not necessary to reserve grooves where a front camera and afacial recognition device are arranged on the display panel. In thisway, the screen production yield is improved.

(2) It is good for designing the comprehensive screen better with thein-cell facial recognition method. In this way, the entire device isbeautified.

(3) It is not necessary to use an additional front camera and anadditional facial recognition device. In this way, the cost of theentire device lessens.

BRIEF DESCRIPTION OF THE DRAWINGS

To describe the technical solutions in the embodiments of thisapplication more clearly, the following briefly introduces theaccompanying drawings required for describing the embodiments.Apparently, the accompanying drawings in the following description showmerely some embodiments of this application, and a person of ordinaryskill in the art may still derive other drawings from these accompanyingdrawings without creative efforts.

FIG. 1 illustrates a schematic diagram of a display panel of the relatedart.

FIG. 2 illustrates a schematic diagram of an in-cell facial recognitiondisplay panel according to a first embodiment of the present disclosure.

FIG. 3 illustrates a cross-sectional diagram of a second embodiment ofan in-cell facial recognition display panel of the present disclosure.

FIG. 4 illustrates a flowchart of panel display and facial recognitionmethod according to a third embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

To help a person skilled in the art better understand the solutions ofthe present disclosure, the following clearly and completely describesthe technical solutions in the embodiments of the present invention withreference to the accompanying drawings in the embodiments of the presentinvention. Apparently, the described embodiments are a part rather thanall of the embodiments of the present invention. All other embodimentsobtained by a person of ordinary skill in the art based on theembodiments of the present invention without creative efforts shall fallwithin the protection scope of the present disclosure.

All of the terminologies containing one or more technical or scientificterminologies have the same meanings that persons skilled in the artunderstand ordinarily unless they are not defined otherwise. Forexample, “upper” or “lower” of a first characteristic and a secondcharacteristic may include a direct touch between the first and secondcharacteristics. The first and second characteristics are not directlytouched; instead, the first and second characteristics are touched viaother characteristics between the first and second characteristics.Besides, the first characteristic arranged on/above/over the secondcharacteristic implies that the first characteristic arranged rightabove/obliquely above or merely means that the level of the firstcharacteristic is higher than the level of the second characteristic.The first characteristic arranged under/below/beneath the secondcharacteristic implies that the first characteristic arranged rightunder/obliquely under or merely means that the level of the firstcharacteristic is lower than the level of the second characteristic.

In the description of this specification, the description of the terms“one embodiment”, “some embodiments”, “examples”, “specific examples”,or “some examples”, and the like, means to refer to the specificfeature, structure, material or characteristic described in connectionwith the embodiments or examples being included in at least oneembodiment or example of the present disclosure. In the presentspecification, the term of the above schematic representation is notnecessary for the same embodiment or example. Furthermore, the specificfeature, structure, material, or characteristic described may be incombination in a suitable manner in any one or more of the embodimentsor examples. In addition, it will be apparent to those skilled in theart that different embodiments or examples described in thisspecification, as well as features of different embodiments or examples,may be combined without contradictory circumstances.

Please refer to FIG. 2 illustrating a schematic diagram of an in-cellfacial recognition display panel according to a first embodiment of thepresent disclosure. The in-cell facial recognition display panelincludes a display area 21 and a non-display area 22. A plurality ofpixels 211 are distributed in an array in the display area 21. Each ofthe plurality of pixels 211 includes a red (R) sub pixel, a green (G)sub pixel, a blue (B) sub pixel, and a facial recognition (F) sub pixel.The F sub pixel is provided with a facial recognition module. The facialrecognition module is configured to capture facial images. One terminalof the non-display area 22 is provided with a display chip 221 and afacial recognition chip 222. The display chip 211 is connected to the Rsub pixel, the G sub pixel, and the B sub pixel, and is configured todrive the R sub pixel, the G sub pixel, and the B sub pixel to performpanel display. The facial recognition chip 222 is connected to the F subpixel and is configured to drive the F sub pixel to capture facialimages.

The facial recognition module is fabricated in an additional F sub pixel(sub pixel F) and configured to capture facial images. At this time,each of the pixels (pixel) includes sub pixel R, sub pixel G, sub pixelB, and sub pixel F. The pixel array is distributed throughout thedisplay area 21. A display chip and a facial recognition chip aredisposed at one terminal of the non-display area 22. The display chipdrives the display panel. The facial recognition chip drives the facialrecognition module.

In another embodiment, a display chip 221 and a facial recognition chip222 may be integrated in the same chip.

Specifically, the plurality of pixels 211 are arrayed in an array. The Rsub pixels, the G sub pixels, the B sub pixels, and the F sub pixels inthe same row are all connected to the same scanning signal line (Gate)through a corresponding thin film transistor (TFT). The R sub pixels inthe same row are separately connected to a first data signal line Data1and are connected to the display chip 221 through the first data signalline Data1. The G sub pixels in the same row are separately connected toa second data signal line Data2 and are connected to the display chip221 through the second data signal line Data2. The B sub pixels in thesame row are separately connected to a third data signal line Data3 andare connected to the display chip 221 through the third data signal lineData3. The F sub pixels in the same row are separately connected to afourth data signal line Data4 and are connected to the facialrecognition chip 222 through the fourth data signal line Data4. That isto say, in the in-cell facial recognition display panel, all of thepixels in the same row share a gate line, and each of the R, G, B, and Fsub pixels has its own data line. The data lines of the R, G, and B subpixels are connected to the display chip. The data lines of the F subpixels are connected to the facial recognition chip.

In the plurality of pixels 211 in an array, the TFTs of all of the R subpixels, the G sub pixels, the B sub pixels, and the F sub pixels in thesame row are turned on upon being connected to the scanning signal linewhich outputs high voltage levels in the same row. The display chip 221inputs display voltage in the corresponding row to the corresponding Rsub pixel in the same row through all of the first data signal linesData1, inputs the display voltage in the corresponding row to thecorresponding G sub pixel in the same row through all of the second datasignal lines Data2, and inputs the display voltage in the correspondingrow to the corresponding B sub pixel in the same row through all of thethird data signal lines Data3. The facial recognition chip 222 readsinformation about the facial images in the corresponding row from thecorresponding F sub pixel in the same row through all of the fourth datasignal lines. In other words, the Gate1 to GateN sequentially outputshigh voltage levels (6V to 12V) to turn on the TFT of the pixel in thecorresponding row. The remaining gate lines are still at low voltagelevels (−9V to −7V) to turn off the TFT of the pixel in thecorresponding row. The display chip connected to the data lines relatedto the R, G, B sub pixels in the corresponding rows feeds displayvoltage in the corresponding row into the data lines related to the R,G, B sub pixels in the corresponding rows. The facial recognition chipreads information about the correct facial images by accessing the dataline related to the F sub pixel in the corresponding row.

Please refer to FIG. 3 illustrating a cross-sectional diagram of asecond embodiment of an in-cell facial recognition display panel of thepresent disclosure. The in-cell facial recognition display panelincludes a display area including a thin film transistor (TFT) arraysubstrate and a color filter (CF) substrate disposed opposite to eachother. The TFT array substrate includes a pixel electrode layer 319. Allpixels are distributed on the pixel electrode layer 319 in an array.Each of the pixels includes an R sub pixel, a G sub pixel, a B subpixel, and an F sub pixel (illustrated as reference numerals R, G, B,and F in FIG. 3) which are separately connected to a thin filmtransistor (TFT). Specifically, the TFT array substrate includes abacklight layer 310, a TFT glass substrate 311, an insulating layer 312,a gate insulating layer (GI) 313, a drain insulating layer (ILD) 314, anorganic flat layer (PLN) 315, a common electrode layer (COM ITO) 316, atouch insulating layer (IL) 317, a display pixel insulating layer (PV)318, and the pixel electrode layer 319, which are all layered on the TFTarray substrate. All of the pixels are distributed on the pixelelectrode layer 319 in an array. The CF substrate includes a CF glasssubstrate 321 and a black matrix (BM) 322 formed on the CF glasssubstrate 321. A third metallic layer M3 is deposited and patterned onthe common electrode layer 316. All of the TFTs are formed on theinsulating layer 312. Specifically, an N-type substrate (a gate of theTFT) is formed on the insulating layer 312 and covers the gateinsulating layer 313. A first metallic layer M1 and a second metalliclayer M2 are deposited on the gate insulating layer 313 and patterned toform a source and a drain of the TFT. The source of the TFT is connectedto a corresponding sub pixel through a hole. The drain of the TFT isconfigured to be connected to a data line. A metallic light shieldinglayer 3121 is arranged on the insulating layer 312 at a positioncorresponding to all of the TFTs. The gate insulating layer (GI) 313 isconfigured to separate the second metallic layer M2 from the gate ofTFT. The drain insulating layer (ILD) 314 is configured to separate thesecond metallic layer M2 from the first metallic layer M1. The organicflat layer (PLN) 315 includes a thicker flat layer which is configuredto fill the unevenness formed by the lower TFT to facilitate fabricationthe circuit on upper layers; The touch insulating layer (IL) 317 isconfigured to separate the third metallic layer M3 from the commonelectrode layer (COM ITO) 316. The touch insulating layer (IL) 317 needsto be punched at a place where the third metallic layer M3 needs to beconnected to the common electrode layer (COM ITO) 316 to make the thirdmetallic layer M3 contact the common electrode layer (COM ITO) 316. Thedisplay pixel insulating layer (PV) 318 is configured to separate thepixel electrode (Pixel ITO) from the third metallic layer M3.

A complementary metal-oxide-semiconductor (CMOS) photosensitivecomponent or a charge coupled device (CCD) photosensitive component isintegrated on each of the F sub pixels and configured to capture images.A three-color photosensitive component, a monochrome photosensitivecomponent, or an infrared photosensitive component can be integrated onthe F sub pixel. Images recognized by the monochrome photosensitivecomponent is black-and-white images. It is not necessary to shine theface 39 with an external light source when the infrared light-sensingunit is used though facial recognition in a dull condition (for example,at night) is realized.

Take facial recognition of monochrome photosensitive component forexample. The face 39 needs to be shined by an external light source,such as sunlight and indoor lighting while facial recognition isconducted. Take sunlight for example, the sunlight reflected by the face39 is incident on the photosensitive component on the F sub pixel, andthe photosensitive component responds, converting the intensityinformation of the reflected light into an electrical signal withcorresponding intensity. The facial recognition chip senses anelectrical signal which each of the F sub pixels corresponds to andconverts the electrical signals into a facial image to capture facialimages completely. Compared the acquired facial images with thepre-stored facial images, and if the same, the facial recognitionpasses; if not, the facial recognition fails. An F sub pixel with afacial recognition module can further be substituted for a front camerafor picture taking.

In another embodiment, each F sub pixel is provided with a thirdmetallic layer M3 under an orthographic projection on a thin filmtransistor (TFT) array substrate 31 for shielding to prevent directillumination of the light in a backlight layer to each of the F subpixels, thereby causing interference in facial recognition.

As for the in-cell facial recognition display panel proposed by thedisclosure, it is necessary to reserve grooves where the front cameraand the facial recognition device are placed, so the screen productionyield of the in-cell facial recognition display panel is enhanced.Besides, the in-cell facial recognition method is beneficial to thedesign of the comprehensive screen, so the entire device is beautified.It is not necessary to use an additional front camera and an additionalfacial recognition device, so the cost of the entire device lessens.

The present disclosure further proposes a liquid crystal display (LCD).The LCD is equipped with a display panel which adopts theabove-mentioned in-cell facial recognition display panel proposed by thepresent disclosure. Specifically, an in-cell facial recognition displaypanel comprises a display area and a non-display area. A plurality ofpixels are distributed in an array in the display area. Each of theplurality of pixels comprises a red sub pixel, a green sub pixel, a bluesub pixel, and a facial recognition sub pixel. The facial recognitionsub pixel is provided with a facial recognition module which isconfigured to capture a facial image. A display chip and facialrecognition chip is arranged at one terminal of the non-display area.The display chip is separately connected to the red sub pixel, the greensub pixel, and the blue sub pixel, and configured to drive the red subpixel, the green sub pixel, and the blue sub pixel to perform paneldisplay. The facial recognition chip is connected to the facialrecognition sub pixel and configured to drive the facial recognition subpixel to capture the facial image.

The present disclosure further proposes a panel display and facialrecognition method. The method is applied to the in-cell facialrecognition display panel proposed by the present disclosure. The methodincludes blocks of sequentially outputting high voltage levels to all ofthe scanning signal lines in the display panel to turn on TFTs which allof the R sub pixels, the G sub pixels, the B sub pixels, and the F subpixels in the corresponding rows correspond to. The display chip inputsthe display voltage imposed on the corresponding row to thecorresponding R sub pixel in the corresponding row through all of thefirst data signal lines. The display chip inputs the display voltageimposed on the corresponding row to the corresponding G sub pixel in thecorresponding row through all of the second data signal lines. Thedisplay chip inputs the display voltage imposed on the corresponding rowto the corresponding B sub pixel in the corresponding row through all ofthe third data signal lines. The facial recognition chip readsinformation about facial images in the corresponding row from thecorresponding F sub pixel in the corresponding row through all of thefourth data signal lines.

The Gate1 to GateN (for example, Gate1920) sequentially outputs highvoltage levels (6V to 12V) to turn on the TFTs of the pixels in thecorresponding row. The remaining gate lines remain low voltage levels(−9V to −7V) to render the TFTs of the pixels in the corresponding rowturn off. The display chip corrected to the data lines related to the R,G, B sub pixel in the corresponding rows feeds correct display voltageinto the data lines related to the R, G, B sub pixel in thecorresponding rows. The facial recognition chip reads information aboutthe correct facial image by accessing the data line related to the F subpixel in the corresponding row.

Please refer to FIG. 4 illustrating a flowchart of panel display andfacial recognition method according to a third embodiment of the presentdisclosure. The method includes block S41, block S42, block S43, andblock S44.

At block S41, at the first moment, corresponding thin film transistors(TFTs) which all sub pixels in a first row correspond to are turned onwith high voltage level output by a first scanning line in a displaypanel. Display voltage is input to a corresponding R sub pixel, acorresponding G sub pixel, and a corresponding B sub pixel in the firstrow through all first data signal lines, all second data signal lines,all third data signal lines, respectively. A facial recognition chipreads information about facial images in the first row from acorresponding F sub pixel in the first row through all fourth datasignal lines.

At block S42, at the second moment, corresponding TFTs which all subpixels in a second row correspond to are turned on with high voltagelevel output by a second scanning line in the display panel. Displayvoltage is input to a corresponding R sub pixel, a corresponding G subpixel, and a corresponding B sub pixel in the second row through all ofthe first data signal lines, all of the second data signal lines, all ofthe third data signal lines, respectively. The facial recognition chipreads information about facial images in the second row from acorresponding F sub pixel in the second row through all of the fourthdata signal lines.

At block S43, at the third moment, corresponding TFTs which all subpixels in a third row correspond to are turned on with high voltagelevel output by a third scanning line in the display panel. Displayvoltage is input to a corresponding R sub pixel, a corresponding G subpixel, and a corresponding B sub pixel in the third row through all ofthe first data signal lines, all of the second data signal lines, all ofthe third data signal lines, respectively. The facial recognition chipreads information about facial images in the third row from acorresponding F sub pixel in the third row through all of the fourthdata signal lines.

At block S44, the blocks will not finish until a last scanning signalline outputs high voltage level to turn on corresponding TFTs which allsub pixels correspond to in a last row. Display voltage is input to acorresponding R sub pixel, a corresponding G sub pixel, and acorresponding B sub pixel in the last row through all of the first datasignal lines, all of the second data signal lines, all of the third datasignal lines, respectively. The facial recognition chip readsinformation about facial images in the last row from a corresponding Fsub pixel in the last row through all of the fourth data signal lines.Then, go back to block S41.

The specific working process of the panel display and facial recognitionmethod according to the present disclosure will be described below bytaking N=1920 as an example.

1) At the first moment, Gate1 outputs a high voltage level to turn oncorresponding thin film transistors (TFTs) which all sub pixelscorrespond to in a first row. Gate2 to Gate1920 output low voltagelevels to turn off corresponding TFTs which all of the sub pixels in theother rows correspond to. At this time, a display chip feeds displayvoltage into all of the sub pixels in the first row through data linesrelated to the R, G, B sub pixels. The facial recognition chip reads theinformation about facial images in the first row through a data linerelated to an F sub pixel.

2) At the second moment, Gate2 outputs a high voltage level to turn oncorresponding TFTs which all sub pixels correspond to in a second row.Gate1 and Gate3 to Gate1920 output low voltage levels to turn offcorresponding TFTs which all of the sub pixels in the other rowscorrespond to. At this time, the display chip feeds display voltage intoall of the sub pixels in the second row through the data lines relatedto the R, G, B sub pixels. The facial recognition chip reads theinformation about facial images in the second row through the data linerelated to the F sub pixel.

3) At the third moment, Gate3 outputs a high voltage level to turn oncorresponding TFTs which all sub pixels correspond to in a third row.Gate1 to Gate2 and Gate4 to Gate1920 output low voltage levels to turnoff corresponding TFTs which all of the sub pixels in the other rowscorrespond to. At this time, the display chip feeds display voltage intoall of the sub pixels in the third row through the data lines related tothe R, G, B sub pixels. The facial recognition chip reads theinformation about facial images in the third row through the data linerelated to the F sub pixel.

4) The working process will not finish until Gate1920 outputs a highvoltage level to turn on corresponding TFTs which all sub pixelscorrespond to in a 1920th row. Gate1 to Gate1919 output low voltagelevels to turn off corresponding TFTs which all of the sub pixels in theother rows correspond to. At this time, the display chip feeds displayvoltage into all of the sub pixels in the 1920th row through the datalines related to the R, G, B sub pixels. The facial recognition chipreads the information about facial images in the 1920th row through thedata line related to the F sub pixel.

Go back to block 1, and repeat block 1 to block 4 again and again.

The above texts are merely specific embodiments of the presentdisclosure. However, the scope of the present disclosure is not limitedhereto. Any variations or alternatives that can easily be thought of bytechnicians familiar with the field should fall within the scope of thepresent disclosure. Therefore, the scope of the present disclosureshould be defined by the scope of the claims.

What is claimed is:
 1. An in-cell facial recognition display panel,comprising a display area and a non-display area wherein a plurality ofpixels are distributed in an array in the display area; each of theplurality of pixels comprises a red sub pixel, a green sub pixel, a bluesub pixel, and a facial recognition sub pixel; the facial recognitionsub pixel is provided with a facial recognition module which isconfigured to capture a facial image; a display chip and facialrecognition chip is arranged at one terminal of the non-display area;the display chip is separately connected to the red sub pixel, the greensub pixel, and the blue sub pixel, and configured to drive the red subpixel, the green sub pixel, and the blue sub pixel to perform paneldisplay; the facial recognition chip is connected to the facialrecognition sub pixel and configured to drive the facial recognition subpixel to capture the facial image, wherein the red sub pixels, the greensub pixels, the blue sub pixels, and the facial recognition sub pixelsin the same row are all connected to the same scanning signal linethrough a corresponding thin film transistor (TFT); the red sub pixelsin the same row are separately connected to a first data signal line andreceive the display chip through the first data signal line; the greensub pixels in the same row are separately connected to a second datasignal line and are connected to the display chip through the seconddata signal line; the blue sub pixels in the same row are separatelyconnected to a third data signal line and are connected to the displaychip through the third data signal line; the facial recognition subpixels in the same row are separately connected to a fourth data signalline and are connected to the facial recognition chip through the fourthdata signal line.
 2. The in-cell facial recognition display panel ofclaim 1, wherein the TFTs of all of the red sub pixels, the green subpixels, the blue sub pixels, and the facial recognition sub pixels inthe same row are turned on upon being connected to the scanning signalline which outputs a high voltage level in the same row; the displaychip inputs display voltage in the corresponding row to thecorresponding red sub pixel in the same row through all of the firstdata signal lines, inputs the display voltage in the corresponding rowto the corresponding green sub pixel in the same row through all of thesecond data signal lines, and inputs the display voltage in thecorresponding row to the corresponding blue sub pixel in the same rowthrough all of the third data signal lines; the facial recognition chipreads information about the facial image in the corresponding row fromthe corresponding facial recognition sub pixel in the same row throughall of the fourth data signal lines.
 3. The in-cell facial recognitiondisplay panel of claim 1, wherein the display area comprises a TFT arraysubstrate and a color filter (CF) substrate disposed opposite to eachother; the TFT array substrate comprises a pixel electrode layer; all ofthe pixels are distributed on the pixel electrode layer in an array;each of the pixels comprises a red sub pixel, a green sub pixel, a bluesub pixel, and a facial recognition sub pixel which are separatelyconnected to a TFT.
 4. The in-cell facial recognition display panel ofclaim 3, wherein a complementary metal-oxide-semiconductor (CMOS)photosensitive component or a charge coupled device (CCD) photosensitivecomponent is integrated on each of the facial recognition sub pixels. 5.The in-cell facial recognition display panel of claim 3, wherein athree-color photosensitive component, a monochrome photosensitivecomponent, or an infrared photosensitive component is integrated on eachof the facial recognition sub pixels.
 6. The in-cell facial recognitiondisplay panel of claim 3, wherein each of the facial recognition subpixels is provided with a third metallic layer under an orthographicprojection on the TFT array substrate.
 7. A panel display and facialrecognition method performed by an in-cell facial recognition displaypanel, wherein the in-cell facial recognition display panel comprises adisplay area and a non-display area, wherein a plurality of pixels aredistributed in an array in the display area; each of the plurality ofpixels comprises a red sub pixel, a green sub pixel, a blue sub pixel,and a facial recognition sub pixel; the facial recognition sub pixel isprovided with a facial recognition module which is configured to capturea facial image; a display chip and facial recognition chip is arrangedat one terminal of the non-display area; the display chip is separatelyconnected to the red sub pixel, the green sub pixel, and the blue subpixel, and configured to drive the red sub pixel, the green sub pixel,and the blue sub pixel to perform panel display; the facial recognitionchip is connected to the facial recognition sub pixel and configured todrive the facial recognition sub pixel to capture the facial image;wherein the panel display and facial recognition method comprises:sequentially outputting a high voltage level to all scanning signallines in the display panel to turn on thin film transistors (TFTs) whichall red sub pixels, green sub pixels, blue sub pixels, and facialrecognition sub pixels in corresponding rows correspond to; inputtingdisplay voltage imposed on the corresponding row with a display chip tothe corresponding red sub pixel in the corresponding row through allfirst data signal lines; inputting the display voltage imposed on thecorresponding row with the display chip to the corresponding green subpixel in the corresponding row through all second data signal lines;inputting the display voltage imposed on the corresponding row with thedisplay chip to the corresponding blue sub pixel in the correspondingrow through all third data signal lines; and reading information about afacial image in the corresponding row with a facial recognition chipfrom the corresponding facial recognition sub pixel in the correspondingrow through all fourth data signal lines.
 8. The panel display andfacial recognition method of claim 7, further comprising: (a) at a firstmoment, turning on corresponding thin film transistors (TFTs) which allsub pixels in a first row correspond to with high voltage level outputby a first scanning line in a display panel; inputting display voltageto a corresponding red sub pixel, a corresponding green sub pixel, and acorresponding blue sub pixel in the first row through all first datasignal lines, all second data signal lines, all third data signal lines,respectively; reading information about a facial image in the first rowfrom a corresponding facial recognition sub pixel in the first row witha facial recognition chip through all fourth data signal lines; (b) at asecond moment, turning on corresponding TFTs which all sub pixels in asecond row correspond to with high voltage level output by a secondscanning line in the display panel; inputting the display voltage to acorresponding red sub pixel, a corresponding green sub pixel, and acorresponding blue sub pixel in the second row through all of the firstdata signal lines, all of the second data signal lines, all of the thirddata signal lines, respectively; reading information about a facialimage in the second row from a corresponding facial recognition subpixel in the second row with the facial recognition chip through all ofthe fourth data signal lines; (c) at a third moment, turning oncorresponding TFTs which all sub pixels in a third row correspond towith high voltage level output by a third scanning line in the displaypanel; inputting the display voltage to a corresponding red sub pixel, acorresponding green sub pixel, and a corresponding blue sub pixel in thethird row through all of the first data signal lines, all of the seconddata signal lines, all of the third data signal lines, respectively;reading information about a facial image in the third row from acorresponding facial recognition sub pixel in the third row with thefacial recognition chip through all of the fourth data signal lines; (d)continuing the blocks until a last scanning signal line outputs highvoltage level to turn on corresponding TFTs which all sub pixelscorrespond to in a last row; inputting the display voltage to acorresponding red sub pixel, a corresponding green sub pixel, and acorresponding blue sub pixel in the last row through all of the firstdata signal lines, all of the second data signal lines, all of the thirddata signal lines, respectively; reading information about a facialimage in the last row from a corresponding facial recognition sub pixelin the last row with the facial recognition chip through all of thefourth data signal lines; afterwards, going back to step (a).
 9. Anin-cell facial recognition display panel, comprising a display area anda non-display area wherein a plurality of pixels are distributed in anarray in the display area; each of the plurality of pixels comprises ared sub pixel, a green sub pixel, a blue sub pixel, and a facialrecognition sub pixel; the facial recognition sub pixel is provided witha facial recognition module which is configured to capture a facialimage; a display chip and facial recognition chip is arranged at oneterminal of the non-display area; the display chip is separatelyconnected to the red sub pixel, the green sub pixel, and the blue subpixel, and configured to drive the red sub pixel, the green sub pixel,and the blue sub pixel to perform panel display; the facial recognitionchip is connected to the facial recognition sub pixel and configured todrive the facial recognition sub pixel to capture the facial image; andthe display area comprises a TFT array substrate and a color filter (CF)substrate disposed opposite to each other; the TFT array substratecomprises a pixel electrode layer; all of the pixels are distributed onthe pixel electrode layer in an array; each of the pixels comprises ared sub pixel, a green sub pixel, a blue sub pixel, and a facialrecognition sub pixel which are separately connected to a TFT.
 10. Thein-cell facial recognition display panel of claim 9, wherein the TFTs ofall of the red sub pixels, the green sub pixels, the blue sub pixels,and the facial recognition sub pixels in the same row are turned on uponbeing connected to the scanning signal line which outputs a high voltagelevel in the same row; the display chip inputs display voltage in thecorresponding row to the corresponding red sub pixel in the same rowthrough all of the first data signal lines, inputs the display voltagein the corresponding row to the corresponding green sub pixel in thesame row through all of the second data signal lines, and inputs thedisplay voltage in the corresponding row to the corresponding blue subpixel in the same row through all of the third data signal lines; thefacial recognition chip reads information about the facial image in thecorresponding row from the corresponding facial recognition sub pixel inthe same row through all of the fourth data signal lines.
 11. Thein-cell facial recognition display panel of claim 3, wherein acomplementary metal-oxide-semiconductor (CMOS) photosensitive componentor a charge coupled device (CCD) photosensitive component is integratedon each of the facial recognition sub pixels.
 12. The in-cell facialrecognition display panel of claim 3, wherein a three-colorphotosensitive component, a monochrome photosensitive component, or aninfrared photosensitive component is integrated on each of the facialrecognition sub pixels.
 13. The in-cell facial recognition display panelof claim 3, wherein each of the facial recognition sub pixels isprovided with a third metallic layer under an orthographic projection onthe TFT array substrate.